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High Performance Current Mode PWM Controller
POWER MANAGEMENT Description
The SC4809A/B/C is a 10 pin BICMOS primary side current mode controller for use in Isolated DC-DC and off-line switching power supplies. It is a highly integrated solution, requiring few external components. It features a high frequency of operation, accurately programmable maximum duty cycle, current mode control, line voltage monitoring, supply UVLO, low start-up current, and programmable soft start with user accessible reference. It operates in a fixed frequency, highly desirable for Telecom applications. Features a separate sync pin which simplifies synchronization to an external clock. Feeding the oscillator of one device to the sync of another forces biphase operation which reduces input ripple and filter size. The SC4809A/B/C have different threshold and VREF to accommodate a wide variety of applications. These devices are available in the MSOP-10 lead free package.
SC4809A/B/C
Features
Operation to 1MHz Accurate programmable maximum duty cycle Line voltage monitoring External frequency synchronization Bi-phase mode of operation for low ripple Under 100A start-up current Accessible reference voltage VDD undervoltage lockout -40C to 105C operating temperature 10 lead MSOP package. Lead free package available. Fully WEEE and RoHS compliant
Applications
Telecom equipment and power supplies Networking power supplies Power over LAN applications Industrial power supplies Isolated power supplies
Typical Application Circuit
+48V
T1
C1 R1 R2 D1 D2 U1 SC4809
1 VDD VREF 10
C7 U2 SC1301
1 IN EN 5
C8
Vout
R3
2
LUVLO
OUT
9
SYNC
3
SYNC
GND
8
2
Q2
GND OUT 4
R12
R13
4
RCT
FB
7
3
VCC
5
DMAX
SS
6
R9
U3 C9
R4
R6
R7
R10 C3 R8 R11
U4 SC4431
R14
R5
Q1 C2 C4 C5 C6
-- 48V
DISABLE
Revision: September 21, 2005
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SC4809A/B/C
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage Supply Current SS, UVLO, DMAX, RCT Current VREF Current LUVLO Storage Temperature Range Junction Temperature Thermal Resistance Lead Temperature (Soldering) 10 Sec. ESD Rating (Human body model)
Symbol V DD IDD
Maximum 19 25 -0.3V to VREF + 0.3V
Units V mA V mA mA C C C/W C kV
IREF ILUVLO TSTG TJ J A TLEAD ESD
15 -1 -65 to +150 -40 to +150 113 +300 2
Electrical Characteristics
Unless specified: VDD = 12V, CSS =1nF, FOSC = 500kHz, RT = 10K, CT = 100pF, DMAX = 2V, TA = TJ = -40C to +105C.
Parameter Supply Section VDD Clamp IDD IDD Starting UVLO Section (A version) Start Threshold Hysteresis UVLO Section (B version) Start Threshold Hysteresis UVLO Section (C version) Start Threshold Hysteresis VREF Section VREF (A version) VREF (B, C version)
Test Conditions
Min
Typ
Max
Unit
16 B version
17.5 1.5
19 2.5 110
V mA A
4.35
4.5 0.3
V V
11
12 4
V V
6.55
6.95 0.75
V V
0 - 5mA 0 - 5mA
-3% -3%
4 5
+3% +3%
V V
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SC4809A/B/C
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VDD = 12V, CSS =1nF, FOSC = 500kHz, RT = 10K, CT = 100pF, DMAX = 2V, TA = TJ = -40C to +105C.
Parameter Line Under Voltage Lockout Start Threshold Hysteresis Input Bias Current Comparator Section IFB Comparator Threshold (A, B version) Comparator Threshold (C version) OUT Propagation Delay (No Load) Soft Start Section ISS Shutdown Threshold (A, B version) Shutdown Threshold (C version) Oscillator Section Frequency range RCT Peak Voltage RCT Valley Voltage Minimum Duty Cycle Pulse Width Maximum Duty Cycle Sync/CLOCK Clock SYNC Threshold Minimum Sync Input Pulse Width Output Section Output VSAT Low Output VSAT High Rise Time Fall Time
Test Conditions
Min
Typ
Max
Unit
RA = 61.9k, RB = 10k RA = 61.9k, RB = 10k LUVLO = 3.2V
-3%
3 150 -100
-3%
V mV
-250
nA
Output Off 570 950 VFB = 0.8V to 1.2V at TR = 10ns
-100 600 1000 75 630 1050 100
nA mV mV ns
VSS = 0V; -40 C -2 300 440 340 500
-8.0
A mV mV
50 3.00 0.05 V FB = 2V 50 90
1100
kHz V V ns %
Positive Edge Triggered FSYNC > Fosc
2.1 50
V ns
IOUT = 1mA IOUT = 1mA COUT = 20pF COUT = 20pF VREF - 0.5 10 10
500
mV V
25 25
ns ns
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SC4809A/B/C
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number SC4809AIMSTR SC4809AIMSTRT(2) SC4809BIMSTR SC4809BIMSTRT(2) SC4809CIMSTR SC4809CIMSTRT(2) MSOP-10 -40C to +150C Package(1) Temp. Range (TJ)
MSOP-10
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
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SC4809A/B/C
POWER MANAGEMENT Pin Descriptions
FB: This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the time capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250 on-resistance NMOS FET during PWM off -time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from the current sense resistor to the FB input and the high frequency filter capacitor capacitance at this node to GND. GND: Reference ground and power ground for all functions. OUT: This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1301). VREF: The internal 4V (A) / 5V (B & C) reference output. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0F ceramic capacitor. RCT: The oscillator frequency is configured by connecting resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT and CT can be selected to provide the desired OUT frequency.
F= 1 V - RT * CT * ln 1 - P -K VREF
DMAX: Duty cycle up to 98% can be programmed via R4 and R5 (the resistor divider from Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle is achieved. SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 8A current source. Under normal soft start SS is discharged to less than 1V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V, soft start is implemented by an increasing output duty cycle. If SS is taken below shutdown threshold, the output driver is inhibited and held low. The user accessible voltage reference also goes low and IDD < 100A. VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1F ceramic capacitor. LUVLO: Line undervoltage lock out pin. An external resistive divider will program the undervoltage lock out level. During the LUVLO, the Driver outputs are disabled and the softstart is reset. SYNC: SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force a out of phase operation. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock with a frequency higher than the on-board oscillator frequency. The external OSC frequency should be 30% greater for guaranteed SYNC operation.
where VP-K = RCT peak voltage
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SC4809A/B/C
POWER MANAGEMENT Block Diagram
Marking Information
Top Mark
AF0A yyww
Top Mark
AF0B yyww
Top Mark
AF0C yyww
Bottom Mark
xxxx xxxx Part Number (Example: 1456) yyww = Datecode (Example: 0012) xxxxx = Semtech Lot # (Example: E901 xxxxx = 01-1)
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Bottom Mark
xxxx xxxx
Bottom Mark
xxxx xxxx
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Q1 FZT458 D1 SD103C
POWER MANAGEMENT Applications Information
R1 750k Z1 BZX84C12 D3 US1B 11 Z3 SMBJ85 R5 510 D2 US1G C5 0.1 U1 SC4809 C12 0.1 U2 SC1301A D4 B240 L2 10uH
L1 (Opt.) T1
90 - 300VDC Np1 Np2
C13 4.7/20V/1.8 Ohm
C1 1/450V
C4 47/400V
C2 2.2n
C3 2.2n
R2 2M
Z2 CMZ5929
R3 820k
1 VDD 9 IN EN 2 GND OUT 4 RCT
R13 300 C14 220pF 7 1 C17 1n R14 100 R15 1.5 U3 MOC207 Vcc C15 0.1 U4 SC4431 C10 1n 5 2 C11 0.33
VREF 1 5
R12 2.2 R16 150 R17 1k R18 3k C16 2.7n Q3 IRFR420
10
+
C19 10uF/6.3V C20 0.1
2 LUVLO 8 4 OUT
C6 100p R6 10k
Ns1
C18 330/6.3V/0.04 Ohm
5V@1A
_
C21 2.2n
R4 100k
3 SYNC 7 VCC 3 GND
FB 6
C9 33n 6
C7 100p
5 DMAX SS
7
R7 7.5k R8 4.3k R9 5.6k
Fsw = 500kHz
R19 10k
R20 316
R10 1k
R21 102
Q2 FMMT718 C8 0.1
R11 3k
CRITICAL COMPONENTS: Q3: IRFR420, Dpak, Inter.Rect. B240, SMB, Vishay C17: 6TPB330M, "7343", Sanyo L2: TOKO, A920CY-100M or similar U1: SC4809AIMSTR, MSOP-10, SEMTECH U2: SC1301AISKTR, SOT-23-5, SEMTECH U4: SC4431CSK, SOT-23-5, SEMTECH
Flyback, 90V - 300V to 5V @ 1A typ.
T1 ----------------------------------------Core: EFD15, 3C85 Magnetizing L = 230uH Np1 = 24 ts Np2 = 5 ts Ns1 = 2 ts Approximate Gap = 0.038mm AL value = 397 nH/N
SC4809A/B/C
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SC4809A/B/C
POWER MANAGEMENT Application Information
The flyback power stage is very popular in 48V input telecom applications for output power levels up to approximately 50 watts. The exact power rating of the flyback power stage, of course, is dependent on the input voltage/output voltage combination, its operating environment and many other factors. Additional output voltages can be generated easily by simply adding another winding to the coupled inductor along with an output diode and output capacitor. Obtaining multiple output voltages from a single power stage is another advantage of the flyback power stage. A simplified schematic of the flyback power stage with a drive circuit block included is shown in Figure 1. In the schematic shown, the secondary winding of the coupled inductor is connected to produce output voltage. The power switch, Q1, is an N-channel MOSFET. The secondary inductance, LSEC and capacitor C, make up the output filter, The resistor R, represents the load seen by the power supply output.
Figure 2: Discontinuous Mode Flyback Waveforms The simplified voltage conversion relationship for the flyback power stage operating in CCM is given by: Figure 1: Flyback Power Converter The important waveforms of the flyback power stage operating in DCM are shown in Figure 2.
VO = VI * NS D * NP 1 - D
The simplified voltage conversion relationship for the flyback power stage operating in DCM is given by:
VO = VI * NS D * NP K
Where K is defined as:
K= 2 * L SEC R * TS
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SC4809A/B/C
POWER MANAGEMENT Application Information (Cont.)
Control-to-Output transfer function for the flyback power stage operating in CCM is given by:
S S 1 + * 1 - dVO N VI z1 z2 = * S * 2 dD (1 - D) NP S S2 + 1+ O * Q O 2
The DC transfer function of a CCM flyback converter is:
VO + VD 1 Dmax = * VIN(min) - VRds( on ) N 1 - Dmax
where VO = output voltage, VD = forward voltage drop across rectifier D1, N = turns ratio, equal to NP/NS, D = duty cycle. Transformer Design The transformer in a flyback converter is actually a coupled inductor with multiple windings. Transformers provide coupling and isolation whereas inductors provide energy storage. The energy stored in the air gap of the inductor is equal to:
E= L P * (IPEAK ) 2
2
where:
1 z1 = RC * C z 2 O Q (1 - D) * R D * L SEC
2
1- D L SEC * C L SEC C
(1 - D) x R
Control-to Output transfer function for the flyback power stage operating in DCM is given by:
N R * TS dVO * = VI * S * NP 2 * L SEC dD 1 1+ S P
where:
P = 2 R*C
where E is in Joules, LP is the primary inductance in Henries, and IPEAK is the primary peak current in Amperes. When the switch is on, D1 is reverse biased due to the dot configuration of the transformer. No current flows in the secondary windings and the current in the primary winding ramps up at a rate of:
IL VIN(min) - VRds( on ) = t LP
Peak current mode control requires simpler compensation, has pulse-by-pulse current limiting, and has better load current regulation. Primary and secondary RMS currents can be up to two times higher for discontinuous mode than for CCM. Discontinuous conduction mode would require using a transistor with a higher current rating. Because the output ripple current is less than it would be continuous mode were used, the output capacitors are smaller. Continuous conduction mode (CCM) was therefore chosen.
The output capacitor, COUT, supplies all of the load current at this time. Because the converter is operating in the continuous conduction mode, IL is the change in the inductor current which appears as a positive slope ramp on a step. The step is present because there is still current left in the secondary windings when the primary turns on. When the switch turns off, current flows through the secondary winding and D1 as a negative ramp on a step, replenishing COUT and supplying current directly to the load.
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SC4809A/B/C
POWER MANAGEMENT Application Information (Cont.)
The primary inductance can be calculated given an acceptable current ripple, IL. IL was set to equal onehalf the peak primary current. For a CCM flyback design, the peak primary current is calculated:
IOUT (max) IPEAK = N 1 * 1- D max IL + 2
MOSFET Selection The switching element in a flyback converter must have a voltage rating high enough to handle the maximum input voltage and the reflected secondary voltage, not to mention any leakage inductance induced spike that is inevitably present. Approximate the required voltage rating of the MOSFET using.
N Vds = (VIN(max) + VL ) + P N S * (VO + VD ) * 1.3
Because the converter is operating in the continuous mode, the maximum peak flux density BMAX, is limited by the saturation flux density, B SAT. Taking all this into consideration, the maximum core size is determined by.
L *I *I * 10 4 AP = P PEAK RMS 420 * k * BMAX
1.31
where Vds = the required drain to source voltage rating of the MOSFET, VL = the voltage spike due to the leakage inductance of the transformer, estimated to be thirty percent of VIN(MAX), and the additions 1.3 factor includes an overall thirty percent margin. This FET will experience both switching and conduction losses. The conduction losses will be equal to the I2R losses, as shown by:
PCOND = (IRMS ) * R DS( ON)
2
where AP = the core area product in cm4, k = winding factor, BMAX BSAT, The result is compared to the product of the winding area, Aw (cm2), and effective core area, Ae (cm2), listed in the core manufacturer's data sheet. The minimum number of primary turns is determined by:
NP = L P * IPEAK * 10 4 B MAX * Ae
Switching losses are the result of overlapping drain current and drain to source voltage at turn on and turn off. The total switching losses are estimated based on equation:
PSW = C OSS * ( VDS )2 * fSW + VDS * IPEAK * t ch * fsw 2
Based upon this result and the predetermined turns ratio, the number of secondary turns is established. The energy stored in the flyback transformer is actually stored in an air gap in the core. This is because the high permeability of the ferrite material can't store much energy without saturating first. By adding an air gap, the hysteresis curve of the magnetic material is actually tilted, requiring a much higher field strength to saturate the core. The length of the air gap is calculated by:
lg = o * r * (NP )2 * Ae * 10 -2 LP
where tch:
t CH = Q gd * R g VDD - Vgs( th )
Diode Selection Schottky rectifiers have a lower forward voltage drop than typical PN devices, making it the rectifier of choice when considering reducing converter losses and improving overall efficiency. Selecting the appropriate Schottky for a specific application depends mainly on the working peak reverse voltage rating and peak repetitive forward current.
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SC4809A/B/C
POWER MANAGEMENT Application Information (Cont.)
Input and Output Capacitors The input capacitors are chosen based upon their ripple current rating and their rated voltage. The actual capacitor value is not that critical as long as the minimum capacitance gives an acceptable ripple voltage determined by the following equation:
CMIN = IRMS 8 * fSW * V
Slope Compensation Sensing peak inductor current instead of average inductor current results in a loop response that is Less than ideal. Adding slope compensation to the current signal cancels this error by maintaining a constant average current independent of duty cycle. Slope compensation is required for open loop stability in a current mode system with 50% or greater duty cycles, but will benefit any current mode application at the cost of a few small parts. Loop Compensation The continuous current mode flyback will contain a righthalf-plane (RHP) zero in its transfer function. Any increase in load current will require the primary peak inductor current to increase. The duty cycle must increase to accomplish this. In a flyback converter, the inductor current flows to the output only when the FET is off and the diode is conducting. Increasing the duty cycle increases the FET condition time but decreases the diode conduction time. The result of this is the average diode current, the current that supplies the load, actually decreases. This is a temporary situation; as the inductor current rises, the diode current eventually reaches its proper value. The condition where the average diode current must actually decrease before it can increase is referred to as a right-half-plane zero. To complicate matters, this zero contributes a phase lag, not a phase lead as a normal zero would. This zero moves in frequency as a function of load and input voltage, making it impossible to cancel out by the insertion of a pole.
N * VIN * L P * ( VIN + N * VOUT )
2
The output capacitors are also chosen based upon their low equivalent series resistance (ESR), ripple current and voltage ratings. The ripple current that the output capacitor experiences is a result of supplying the load current during the FET conduction time and its charging current during the FET off-time. Voltage Feedback The FB pin of the SC4809 sums the voltage feedback signal to the current sense signal and any added slope compensation. The voltage feedback signal is from an optocoupler, which is driven from an error amplifier on the secondary side of the converter. The signal from the optocoupler is designed to trip the FB threshold of the SC4809 internal comparator when the output voltage exceeds its specified limit. Current Limit Selection of the current sense resistor is accomplished by dividing the FB threshold value by the peak primary current at the desired current limit point. This groundreferenced RSENSE must be a low inductance type and have a rated power level to meet the (I RMS ) 2* R SENSE requirement. Current spikes caused by the leakage inductance of the flyback transformer and the reverse recovery of the diode could trip the current sense latch and prematurely shut off the output. This unwanted spike can be suppressed by adding a small RC filter for effective leading edge blanking.
fRHPZERO =
2 * * R OUT
The easiest way to deal with a right-half-plane zero is to roll off the loop gain at a relatively low frequency using simple dominant pole compensation. Unfortunately, the result of this is poor dynamic response. The primary goal of the compensation network is to provide good line and load regulation and dynamic response. These objectives are best met by providing high gain at low frequencies for good DC regulation and high bandwidth for good transient response. Optimum closed loop performance can only be achieved by first
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SC4809A/B/C
POWER MANAGEMENT Application Information (Cont.)
knowing what the transfer characteristic of the PWM and switching circuit looks like. Constructing a Bode plot of the known poles and zeros in the power stage does this. Bode plots give a visual interpretation of the gain versus frequency and phase versus frequency characteristics of a system. In the gain plot, the gain shown at each frequency represents the amount by which the feedback loop will reduce a disturbance at that frequency. Besides the RHP zero, the output capacitor and the load contribute a pole and the output capacitor alone will contribute a zero based upon its ESR.
fpole = 1+ D 2 * * R OUT * C OUT 1 2 * ESR * C OUT
The scheme shown below will handle most compensation requirements. There is a pole at the origin which contributes a -1 slope in the gain plot, a low frequency zero, fEAZERO flattens out the slope so the mid-range gain is equal to Rf/Ri. A high frequency pole, fEAPOLE helps suppress any high frequency noise from propagating through the system. Rd forms a voltage divider with Ri and provides a DC offset.
1 2 * * R f * Cf 1 2 * * R f * Cp
fEAZERO = fEAPOLE =
f zero =
The control to output gain is calculated by:
ISC * R OUT * VIN GAIN = 20 * log* VC * (1 - D) * (2 * N * VO + VIN )
Once the frequency response of the uncompensated system is determined, the next step is to determine what compensation is needed around the error amplifier for optimum performance. As stated earlier, optimum performance requires a high gain at low frequencies for good DC regulation and high bandwidth for good transient response. The crossover frequency, fc, is the frequency at which the gain magnitude equals 0dB. High bandwidth is achieved by having the highest possible fc. Because of the RHP zero, the highest possible crossover frequency is limited to fRHPZERO/. The phase margin, or the amount the phase lag measures at fc less 180, should be at least 45 for good transient response with little overshoot. The magnitude of the gain at the frequency where the phase plot measures - 180 is referred to as the gain margin. If the slope of the gain plot is -2, or -40dB/decade, at low frequencies, it much transition to a -20dB/decade slope, also known as a -1 slope, one decade before crossing the 0dB point. If the slope remains at the -2 slope the resultant gain margin would be too small causing sever underdamped oscillations at fc.
By combining the Bode plots of the PWM and power stage with the error amplifier compensation, a plot of the entire system is realized.
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Ra 300 1W
Qa TIP30C
Rb 300 1W
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GND C1 1.0/100V R2 20k R9 100 U1 SC4809 C7 0.1 VREF OUT EN 3 SYNC OUT 4 RCT DMAX R15 22k R11 7.5k R4 2.7k R6 10k R8 3.9k R12 1k R16 47k R7 1k C3 0.47 SS 6 R10 47k Q2 IRF640N FB VCC 5 7 3 Q3 BSS64ZXCT 4 C9 1n GND GND R13 10 8 2 5 Z2 ZMM5242B 9 IN 1 10 U2 SC1301 +12V 2 LUVLO C8 1.0 D1 MURD620CT Z1 ZMM5242B 1 VDD R3 1k L1 10uH R17 1k C10 150/16V C11 1.0 R18 200 1W
Za ZMM5242B
R1 1k
POWER MANAGEMENT Applications Information (Cont.)
"SLAVE"
R5 7.5k C2 150p C4 0.1 C5 C6 0.47 200p
Q1 MMBT2907A
R14 0.2 1/2W
DISABLE
13
C1 1.0/100V R2 20k R9 100 U1 SC4809 C7 0.1 VREF OUT GND FB SS 6 7 8 9 1 2 3 10 Z1 ZMM5242B U2 SC1301 IN EN 3 SYNC RCT DMAX 4 5 GND OUT VCC R10 47k R11 7.5k R4 2.7k R6 10k R7 1k C3 0.47 R8 3.9k R12 1k Q2 IRF640N 4 5 R13 10 C8 1.0 1 VDD LUVLO R3 1k 2 L1 10uH R5 7.5k C2 100p Q1 MMBT2907A C4 0.1 C5 C6 0.47 200p R14 0.2 1/2W DISABLE
+48V
GND
R17 1k
C10 150/16V
C11 1.0
R18 200 1W
D1 MURD620CT +12V Z2 ZMM5242B C9 1n Q3 BSS64ZXCT R15 22k
"MASTER"
Out of Phase, Synchronized, Dual Converter
R16 47k
SC4809A/B/C
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-- 48V
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C10 1.0/16V
6 R14 3.3k 1W
1
C1 R12 * R11 100 D2 ES1D
3 2 7,8,9 4 SMA
POWER MANAGEMENT Evaluation Board Schematic
1.0/100V R19 20 1/4W L1 2.5uH@10A C14-16 470/6.3V C17 10.0 C13 1nF/50V
R3 100k
C11 0.01/100V
C2 0.01 U1 SC4809_A_B_C
1 VDD EN 2 LUVLO OUT 3 SYNC GND VCC 8 3 4 OUT GND 9 2 5
10,11,12
Z1 ZMM5245B C9 1/25V U2 SC1301A
1 IN
R4 10k R15 3.3 Q3 IRF640NS R20 1k
C3 0.1/25V
VREF 10
D3 MBRB1530CT
SYNC
4 RCT FB 7
R21 1k R22 39.2k
R25 3.83k R26 0 R23 62k
R5 10k R16 *
5 6 7 1 2
U3 MOC207
14
5 DMAX SS 6
R1 5.1k
Q1 MMBT2222A
Q2 MMBT2907A
Fsw=330kHz
C6 0.033 C8 * R18 *
R17 *
Vcc C7 0.47 C12 220pF C18 0.022 U4 SC4431 C19 0.01
C20 430pF
C21 0.01
R2 1k
R7
C4 *
10k
R8 1.5k R9 7.5k
R24 1.21k
R6 2k
R10 * C5 0.01
50W Forward Converter
T1: PA0273, Pulse Eng.
R18 R12 2x12k| | 3x12k| | 2x10k| | 300p 390p 300p 680p 200p 680p 0.15 0.15 0.22 C4 C8
R10
R16
R17
L1: ETQP6F2R5SFA, Panasonic C14-16: 6TPB470M, PosCap, Sanyo
A
10k
62
604
B
10k
62
604
SC4809A/B/C
C
8.2k
100
1k
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SC4809A/B/C
POWER MANAGEMENT Evaluation Board Layout
50W Forward Converter
Layout
Top
Bottom
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SC4809A/B/C
POWER MANAGEMENT Outline Drawing - MSOP-10
e A N 2X E/2 PIN 1 INDICATOR ccc C 2X N/2 TIPS 12 B E1 E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 8 0 .004 .003 .010 1.10 0.00 0.15 0.75 0.95 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0 8 0.10 0.08 0.25
D aaa C SEATING PLANE A2 C A1 bxN bbb C A-B D A GAGE PLANE 0.25 (L1) DETAIL SIDE VIEW SEE DETAIL L H c
01
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp.
16
www.semtech.com

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